A Clock and Data Recovery Circuit for Optical Communications in 0.18 m CMOS

The amount of data transmitted over the global communications networks has experienced a dramatic increase over the last years, mainly driven by the exponential growth of the Internet. For this reason, increasingly faster and more reliable circuits are needed to allow a correct performance at speeds in the range of the Gbps. The superior power characteristics and overall performance make optical fiber the preferred choice to implement the channel in communications links, giving rise to the concept of optical communications. Due to their bandwidth limitations, in a typical optical communcations link data cannot be transmitted with a timing reference; the clock signal that allows its correct interpretation has to be extracted at the receiver in a block called clock and data recovery circuit (CDR). Typically, a CDR circuit is a closed-loop system that generates an oscillating signal capable of tracking the phase of the incoming data stream; as well, it uses the generated clock signal to regenerate the data stream, minimising the effects of non-idealities during transmission. This paper presents the design of a CDR circuit intended to meet the 10GBase-LX4 Ethernet specifications for continuous operation at 3.125 GHz, designed in a standard 0.18 m CMOS technology provided by UMC. A detailed description of the full CDR circuit and the different blocks taking part in it will be provided, emphasising the requirements that each of them must satisfy. Finally, the correct performance of the proposed CDR circuit will be analysed by means of an extensive set of post-layout simulations

High-sensitivity large-area photodiode read-out using a divide-and-conquer technique

In this letter, we present a novel technique to increase the sensitivity of optical read-out with large integrated photodiodes (PD). It consists of manufacturing the PD in several pieces, instead of a single device, and connecting a dedicated transimpedance amplifier (TIA) to each of these pieces. The output signals of the TIAs are combined, achieving a higher signal-to-noise ratio than with the traditional approach. This work shows a remarkable improvement in the sensitivity and transimpedance without the need for additional modifications or compensation techniques. As a result, an increase in sensitivity of 7.9 dBm and transimpedance of 8.7 dBO for the same bandwidth is achieved when dividing the photodiode read-out into 16 parallel paths. The proposed divide-and-conquer technique can be applied to any TIA design, and it is also independent of the core amplifier structure and fabrication process, which means it is compatible with every technology allowing the integration of PDs

Synchronous OEIC integrating receiver for optically reconfigurable gate arrays

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35µm opto-CMOS process fed at 3.3V and due to the highly effective integrated pin photodiode it operates at µW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of -26.0dBm and -25.5dBm are achieved, respectively, for ¿ = 635nm and ¿ = 675nm (BER =10-9) with an energy efficiency of 2 pJ/bit

Programmable low-power low-noise capacitance to voltage converter for MEMS accelerometers

In this work, we present a capacitance-to-voltage converter (CVC) for capacitive accelerometers based on microelectromechanical systems (MEMS). Based on a fully-differential transimpedance amplifier (TIA), it features a 34-dB transimpedance gain control and over one decade programmable bandwidth, from 75 kHz to 1.2 MHz. The TIA is aimed for low-cost low-power capacitive sensor applications. It has been designed in a standard 0.18-µm CMOS technology and its power consumption is only 54 µW. At the maximum transimpedance configuration, the TIA shows an equivalent input noise of 42 fA/vHz at 50 kHz, which corresponds to 100 µg/vHz

Application of a flipped classroom for model-based learning in electronics

This paper investigates the effectiveness of the flipped classroom methodology to build conceptual knowledge mentalmodels. In particular, it examines the learning process and outcomes of 40 students of a course on Physical Electronics inthe last year of a bachelor’s degree program in Physics, for which specific educational resources have been developed toimplement the flipped classroom. Among them, non-interactive resources are better to present topics and ideas, whereasinteractive resources are more useful to establish links between them to build and check the models. The examined dataentail grades, laboratory reports and rubrics, outcomes of learning activities, and direct observation, showing that theflipped classroom improves the construction of mental models, providing teaching resources where the topics and mainideas are presented, developed and exercised, and allowing students to establish links to build and check the models.Furthermore, this strategy increases the personal commitment of the students, fostering autonomy and cooperation withpeers, all of which makes it an effective pedagogical tool to build knowledge mental models

ICT-based didactic strategies to build knowledge models in electronics in higher education

This paper presents a didactic strategy based on information and communication technologies (ICTs) to help students build knowledge mental models in the context of Higher Education. It presents a methodology that combines the flipped classroom with other active methodologies and traditional lessons to improve the teaching/learning process of Electronics in university studies in Physics. Using the flipped classroom as the main strategy, the proposed methodology allows devoting more classroom time to active learning so that the instructor can follow the student learning process and evaluate model construction, while at the same time it increases student implication and fosters autonomy and cooperation with peers, contributing to a better construction of knowledge mental models in Electronics

CMOS Duobinary Transceiver for Multigigabit Communications

This work presents a CMOS transceiver for amplitude duobinary modulation over an equalized 50-m step-index plastic optical fiber (SI-POF). Both duobinary precoder and decoder have been fabricated in 0.18-μm CMOS technology, enabling a bandlimited system of 700 MHz to operate at 3.125 Gbps with a consumption of 28.4 mW

Improved Precoder Architecture for Duobinary Transceivers

Duobinary modulation is an attractive baseband modulation scheme for high-speed serial data transmission. This work presents a duobinary transceiver with a new precoder architecture that overcomes the glitch vulnerability of the conventional ones. It has been fabricated in a 0.13-μm PD-SOI CMOS technology and achieves 10 Gbps consuming 37 mW.

Physical Layer Encryption for Industrial Ethernet in Gigabit Optical Links

Industrial Ethernet is a technology widely spread in factory floors and critical infrastructures where a high amount of data need to be collected and transported. Fiber optic networks at gigabit rates fit well with that type of environment, where speed, system performance, and reliability are critical. In this paper, a new encryption method for high-speed optical communications suitable for such kinds of networks is proposed. This new encryption method consists of a symmetric streaming encryption of the 8b/10b data flow at physical coding sublayer level. It is carried out thanks to a format preserving encryption block cipher working in CTR (counter) mode. The overall system has been simulated and implemented in a field programmable gate array. Thanks to experimental results, it can be concluded that it is possible to cipher traffic at this physical level in a secure way. In addition, no overhead is introduced during encryption, getting minimum latency and maximum throughput

A new simple technique for improving the random properties of chaos-based cryptosystems

A new technique for improving the security of chaos-based stream ciphers has been proposed and tested experimentally. This technique manages to improve the randomness properties of the generated keystream by preventing the system to fall into short period cycles due to digitation. In order to test this technique, a stream cipher based on a Skew Tent Map algorithm has been implemented on a Virtex 7 FPGA. The randomness of the keystream generated by this system has been compared to the randomness of the keystream generated by the same system with the proposed randomness-enhancement technique. By subjecting both keystreams to the National Institute of Standards and Technology (NIST) tests, we have proved that our method can considerably improve the randomness of the generated keystreams. In order to incorporate our randomness-enhancement technique, only 41 extra slices have been needed, proving that, apart from effective, this method is also efficient in terms of area and hardware resources